3.2T DSP Architecture for Cohernet Optical Transmission Applications - ON-161

Preferred Disciplines: Electrical engineering, Mathematics (Masters, PhD or Post-Doc)
Company: Anonymous
Project Length: 8-16 months (2-4 units)
Desired start date: As soon as possible
Location: Ottawa, ON
No. of Positions: 4
Preferences: None

About the Company: 

Partner is an R&D company involved in the development of Intellectual Property for Networking and security (data communications telecommunications and Wireless).

Project Description:

Ultra long haul optical networks require high gain, high preformance DSP  designs capable of achieving line speeds ranging from 400Gb/s to 3.2Tb/s for the telecom market.

As long haul and ultra long haul appliction impose less restriction on real estate, this DSP algorithm needs to achieve the performance requirements for most ultra long haul optical transmission applications. Hence, a novel hardware (algorithm) deisgn must be innovatively researched and developed.

This design is expected to be propriertary, and in a true system the DSP Modules will be used in book ended implementations (Tx-Rx matching at both ends).

In addition to the performance requirement, the DSP module/design must be mapped onto FinFET process, therefore, a smaller design foorprint is desired as it is advantageous for comercialization.

The detail requirements of the DSP target paramters will be provided by the partner company.

Research Objectives:

  • Understand the existing architecture of Cohernet DSP.
  • Identify/Create new architectures using the a new or novel DSP algorithm to achieve the optimal power and highest performance acheiveable.
  • Select the most efficient architecture for FinFET process.
  • The algorithm must be verified using Matlab or C code for best power and performance.
  • The algorithm must be implementable in hardware (ASIC).
  • The algorithm must meet a predetermined power target for an (ASIC).


  • Identify the architectures for the DSP optimized for foot print and performance.
  • Create C or C++ module for verification and modeling.
  • Create behavioral modeling in Verilog or VHDL for fast simulation.
  • Implement the module using Verilog or VHDL using synthesizable construct.
  • Create simulation environment to verify the design using System Verilog/C/etc.
  • Implement the design in FPGA and validate the algorithm in real FPGA hardware.
  • The design must meet the industrial standard for telecommunication.

Expertise and Skills Needed:

    • DSP knowledge for telecommunciations and Cohernet modem appliactions.
    • Knowledge of DSP archietecure.
    • DSP performance modeling.
    • Matlab/Octave modeling and simulation.
    • Logic design using Verilog or VHDL.

    For more info or to apply to this applied research position, please

    1. Check your eligibility and find more information about open projects
    2. Interested students need to get the approval from their supervisor and send their CV along with a link to their supervisor’s university webpage to Mel Chaar.