Low power FEC architecture using HD Staircase FEC and SD Hamming Code - ON-126

Preferred Disciplines and Level: Electrical engineering, Mathematics and level Master, PhD, Post-Doc
Company: NA
Project Length: 8-24 months each (2-4 units each)
Desired start date: As soon as possible
Location: Ottawa, Ontario
No. of Positions: 4
Preferences: Language: English        

About the Company: 

Partner is an R&D company involved in the development of Intellectual Property for Networking and security (data communications telecommunications and Wireless) 

Project Description:

The Project is to develop a ultra low power and high gain concatenated FEC using hard decision Staircase FEC and soft decision Hamming code for 400-500Gb/s telecom application. A novel algorithm is needed to meet the low power requirement as well as meet the NCG of the standard. In addition to the NCG requirement, the whole module or design of the Concatenated FEC must be mapped onto FinFET process. The polynomials of the FEC and the standard to be used will be provided by the partner company.

Research Objectives:​

  • Understand the existing architecture of Staircase FEC and Hamming Code and their effect of concatenating them together
  • Identify/Create new architectures using the Staircase FEC and Hamming Code to achieve the optimal power and highest NCG requirement
  • Select the most efficient architecture for FinFET process
  • Simulate the selected architecture and verify it against Matlab/Octave/C++ model
  • Implement the entire Concatenated FEC module and verify it meet the NCG, timing and power requirements
  • Prove the Concatenated FEC module on FPGA hardware for the NCG


  • Stress the research-related approaches here
  • Identify the architectures of the HD FEC and SD Hamming using Matlab/Octave
  • Create C or C++ module for verification and modeling
  • Create behavioral modeling in Verilog or VHDL for fast simulation
  • Implement the module using Verilog or VHDL using synthesizable construct
  • Create simulation environment to verify the design using SystemVerilog/C/etc
  • Implement the design in FPGA and validate the algorithm and NCG in real FPGA hardware
  • The design must meet the industrial standard for telecommunication.

Expertise and Skills Needed:

  • Soft-decision and hard decision FEC knowledge
  • Knowledge of Staircase FEC and Hamming Code
  • FEC performance modeling
  • Matlab/Octave modeling and simulation
  • Logic design using Verilog or VHDL

For more info or to apply to this applied research position, please

  1. Check your eligibility and find more information about open projects.

  2. Interested students need to get the approval from their supervisor and send their CV along with a link to their supervisor’s university webpage directly to Mel Chaar, mchaar(a)mitacs.ca.