Experimental Computer-Aided Design Flow
Field-Programmable Gate Arrays (FPGAs) have become the implementation medium of choice for many digital circuits in areas as diverse as telecommunications, bioinformatics, visualization systems, and digital signal processing. One of the few areas where FPGAs have not yet become ubiquitous is in mobile applications.This application area is huge; together with cloud computing, we expect that mobile devices will become the computing platform of the future. These devices will represent much more than email and web platforms; they will provide personal and immediate computing applications that will aid, heal, inform and empower humanity in the next few decades. The primary reasons that Field-Programmable Gate Arrays have not been employed in mobile devices is their energy dissipation and cost. In this project, we will investigate (a) new energyefficient FPGA architectures, (b) a method for mapping applications to FPGAs with energy as a first-class concern, and (c) an understanding and demonstration of what is possible in a mobile device enhanced with our programmable platform. We have partnered with Altera, a major FPGA vendor with a significant R&D presence in Toronto, who would be able to immediately employ our techniques to produce better FPGAs.
We will explore and develop energy-aware CAD algorithms and software tools that can map circuits to the architectures proposed in (a). We will engage in an extensive collaborative effort, building on  whose purpose is to enable FPGA architecture and CAD research based on applications designed at the Verilog HDL level. This CAD flow consists of HDL elaboration, logic optimization, technology mapping, clustering, placement, and routing. Our prior research has identified energy-efficient methods for several of these steps [SW15;2]; however, this did not consider the novel features proposed in Task 1. In addition, we have not considered energyefficient elaboration, which is essential to make effective use of these energy-savings features. The energy-savings features of an FPGA must be designed to be general-purpose and suit as many applications as possible. This is a fundamental difference between reducing power in a fixed-function chip compared to an FPGA. For a fixed-function chip, the designer can examine the application, and create voltage islands or other power-saving structures that are optimized specifically for that application. When mapping the application to an FPGA, however, the
designer must use the collection of power-savings features available on the FPGA in a judicious manner. In this project, we will seek methods to automate the translation of the application’s power requirements to the implementation of those requirements using the available FPGA poweroptimization features. The methods will be encapsulated in a Power Elaboration algorithm and tool.