FPGA-based Design, Evaluation and Prototyping of Power Management Strategies for Multi-core Processors

Single chip multi-core processors have become the de-facto computational platform for application domains ranging from low-power mobile and embedded devices to high-end server products that form the backbone of the worldwide information technology (IT) infrastructure. Power management has always been an issue in the mobile computing space, and with the alarmingly increasing rates of energy consumption in data centers (an estimated 100 billion kWH by 2011), it has become a critical need in high-end server market as well. To provide fine-grained power management capabilities, multi-core systems are increasingly being instrumented with a number of on-chip control knobs that can be used to dynamically vary the power-performance characteristics of the chip.

In this project, we plan to use FPGA prototyping to experimentally study a wide range of multi-core power management and elucidate the merits and demerits of these schemes. This study is enabled by the fact that current top-of-the-line FPGA boards  provide the capability to map a large number of programmable cores on the FPGA and also allow for each core to be instantiated in a separate clock domain. Starting with this multi-core, multi-clock domain FPGA platform, we will develop synthesizable HDL (either Verilog or VHDL) code for the power management algorithms and map them on the FPGA. We will then program a variety of parallel applications on the FPGA cores and study how the various power management algorithms perform in terms of (i) ability to minimize power for a given performance target; (ii) implementation costs, i.e., area and routing overheads; and (iii) scalability. We intend to make the HDL and application code developed during the course of this project freely available on our website to spur further research in this area.

Intern: 
Sundaram Ananthanarayanan
Faculty Supervisor: 
Dr. Siddharth Garg
Province: 
Ontario