Probabilistic based Ultra-low Supply Voltage Noise Tolerant Circuits and Systems Design
As very large scale integrated circuit (VLSI) technology progresses, power consumption and power density of VLSI circuits increase when design complexity and transistor density increase. Low-power design becomes a major design challenge. Lowering the supply voltage is one of the most efficient ways to save power because power consumption is proportional to the square of supply voltage. Electronic devices are expected to operate at much a lower supply voltage than traditional designs, which is very useful for portable electronics and biomedical implants. Unfortunately, when supply voltage decreases, soft faults (e.g., noise and cross talk) does not decrease proportionally. For instance, one of the major challenges in ultra low-power and deep-submicrometer circuit design is noise fluctuation. Ultra deep-submicrometer VLSI circuits are expected to operate at much smaller noise margins, and thus, VLSI circuits are more sensitive to soft faults. In this project, a probabilistic-based fault-tolerant circuit design methodology based on Markov Random Field (MRF) theory is proposed. This iPDF grant is to support the applicant to team up with the industrial partner in applying the MRF-based design methods to implement large-scale signal processing and communication systems.