Ciena OPn Innovation WP 1.1.6 - High Speed Low Power Transceiver

The intent of this project is to address the high-speed electronic portion of a silicon photonic transceiver solution that will explore new and innovative metro reach terabit optical modems. In total there are five projects that combine to create the solution. These five project areas are silicon photonic design, high-speed electronic design, modelling, packaging and test.
The throughput of Ciena’s next generation optical modems is approaching a Terabit per second, transporting data within the chip, across different dies within the same package, and between different modules on the card is becoming one of the limiting bottlenecks to our systems. To overcome this limit a 100Gb/s capable SERDES is required. Indeed, the next frontier that needs to be surpassed is a design of SERDES link in the most economical way in terms of power and real-estate. Our world-class analog/mixed-signal design team at Ciena has expertise covering high-speed data converters, multiplexors, de-multiplexors PLLs and CDRs. In this project the collaboration will be between Ciena and Prof. Mohamad Sawan, from Polytechnique Montréal. This research project will focus on designing, implementing and testing high-speed data transmitters.

Intern: 
Milad Salehi
Superviseur universitaire: 
Mohamad Sawan
Province: 
Quebec
Partenaire: 
Partner University: 
Programme: