RISC-V validation internship

This project focuses on improving the trustworthiness of a RISC-V processor design intended for use in aircraft systems by carefully checking that it works correctly and securely. Modern aircraft depend heavily on software and digital hardware, so even small design errors or hidden security weaknesses can create safety risks. The project will verify a security-enhanced RISC-V core using a mix of testing, formal checks, and FPGA prototyping to confirm that it behaves as expected and that the added security features do not interfere with normal operation. By following practices aligned with avionics assurance standards, the work will produce clear verification evidence, coverage results, and reusable tools. Participating institutions benefit by gaining a validated processor prototype, hands-on experience with high-assurance verification methods, and documented results that can support future research, teaching, and certification-oriented development in safety-critical and secure computing systems.

Faculty Supervisor:

Felipe Gohring de Magalhaes

Student:

Partner:

École des Mines de Saint-Étienne

Discipline:

Computer science

Sector:

Aerospace; Cyber Security

University:

Polytechnique Montréal

Program: