WP 1.1.7 – High Speed and SPIC Packaging and Signal Integrity

The intent of this project is to address the high-speed electronic and photonic packaging portion of a silicon photonic transceiver solution that will explore new and innovative metro reach terabit optical modems.
Packaging is of utmost concern with regard to achievable optical modem performance and eventual costs. Ciena’s optical transceiver performance and cost will be defined by the quality of the packaging solution and the integrity of the signals from electrical dies, to silicon photonic, to module, then board interconnect. Packaging and signal integrity constraints have to be considered very early in the design and cannot be considered as an afterthought after the system has been architected and the chips are well in the design process.

In this project we would like to explore new and innovative packaging techniques for integration of electrical high bandwidth ICs and photonic ICs. The following will be explored very early in the architecture phase of the design:
• Micro ball
• 3D integration using TSV or TGV
• Interposer and MCM
• Power plane and signal integrity for high speed/high power CMOS chips
• Silicon photonic integrated circuit packaging

Faculty Supervisor:

Ammar Kouki

Student:

Partner:

Ciena Canada (Saint-Laurent, QC)

Discipline:

Engineering

Sector:

Information and cultural industries; Manufacturing

University:

École de technologie supérieure

Program: