Fault injection framework to study the soft error resilience of FPGA based systems

Soft errors are known to have a significant impact on circuit reliability. When high energy particles from either cosmic rays or packaging materials strike a semiconductor substrate, they generate charge which in turn results in a glitch or a transient current in a circuit. Such a glitch is called the single event transient (SET). The SET can occur on a register or on a logic gate in a circuit and can propagate to eventually get captured in a register, altering the stored bit. Such an error is known as a single event upset (SEU) or soft error.
FPGAs are widely used in applications such as industrial, aircrafts, space crafts, high-end computing systems due to their high performance, easy reconfigurability, quick time to market and low cost. FPGA-based designs are more susceptible to soft errors compared to ASIC designs as they contain more memory elements. Soft error rate (SER) estimation is a crucial step in the design of soft error tolerant schemes to attain the required reliability and performance of the system. Existing studies focus mainly on single bit-upsets and mitigation schemes. TBC

Faculty Supervisor:

Otmane Ait Mohamed

Student:

Partner:

International Institute of Information Technology Bangalore

Discipline:

Engineering

Sector:

Education

University:

Concordia University

Program: