Development of a Timing-Enhanced AXI Protocol Tracing Solution for FPGA

The proposed project aims to enhance Ciena’s existing AXI protocol tracing solution for FPGAs by adding a timing feature through synchronized counters. This improvement will allow for more accurate data flow tracking and performance within FPGA systems. By integrating this timing capability, the enhanced module will provide Ciena with better diagnostics and debugging tools, leading to more efficient and reliable product development. This project helps the intern gain valuable experience and offers a significant technical upgrade for Ciena’s FPGA-based solutions.

Faculty Supervisor:

Tarek Ould-Bachir

Student:

Partner:

Ciena Corporation (St-Laurent, QC);Ciena Corporation (Ottawa, ON)

Discipline:

Engineering

Sector:

Manufacturing

University:

Polytechnique Montréal

Program:

Business Strategy Internship

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