RTL Implemetation of an HDC accelerator

This project aims to develop an RTL model for a programmable accelerator for hyperdimensional computing (HDC), a brain-inspired approach that uses high-dimensional vectors for data processing. HDC is particularly suitable for resource-constrained environments because it avoids complex matrix multiplications, relying instead on efficient bitwise operations that can be implemented on hardware like FPGAs or ASICs. By optimizing the encoding process, which transforms input data into high-dimensional vectors, the accelerator will improve accuracy and adaptability across various applications, including image and voice recognition. The project’s benefits for the participating institutions include advancing their expertise in hardware acceleration for AI and embedded systems, and enhancing their capacity for innovative, sustainable computing solutions.

Faculty Supervisor:

Sébastien Le Beux;Otmane Ait Mohamed

Student:

Partner:

Télécom Saint-Étienne

Discipline:

Engineering

Sector:

Information and Communications Technology

University:

Concordia University

Program: