Hierarchical Thermal Transport in Electronic Devices: Nano-Scale and Transistor-Level Modelling
The conventional continuum-based physical relations that describe heat and fluid flow in bulk materials, such as the Navier-Stokes and Fourier equations, break down at sub-continuum scales. The failure of these relations, along with the current trend of miniaturization in man-made devices and wide spread use of nano-structured systems, urge for development of new computational techniques capable of modelling sub-continuum physical phenomena. This project specifically studies the thermal transport modelling in nano‐structured systems.
The proposed project is a part of an ongoing collaboration with an industry partner (Advanced Micro Devices, AMD Inc.) and academic collaborators at University of Texas at Arlington and State University of New York at Binghamton. The overall objective of the project is to provide a computational framework for thermal transport prediction in electronic devices that hierarchically incorporates physics-based models at different lengths from nano to macro scales.
The Globalink student will work on the transistor level modelling. The three-dimensional transistor structure is reconstructed based on the technology used in the current AMD devices using a CAD software. The model includes gate, drain, source, and metal interconnects of the transistor. The reconstructed geometry will be then imported into a computational heat transfer software, e.g., ANSYS, and the temperature distribution inside the transistor components is calculated for different boundary conditions and various working conditions. Using these simulation data, we develop a compact model for the average temperature of a transistor as a function of average temperatures of neighbouring transistors and working conditions. This compact model for a single transistor will be used to model the next length-scale level in the hierarchy, which is the functional block level. Once the thermal transport at the functional block level is achieved, optimization algorithms are applied to find the optimal positioning of these functional blocks on the die surface.
