Multi-channel GNSS Signal Simulation Using CPU/GPU Platforms and FPGA-based Digital Signal Processing Cards
Currently the implementation of navigation information systems – sometimes called “GPS” or GNSS (Global Navigation Satellite Systems) for convenience – is undergoing some significant transitions. Additional satellite constellations are being proposed and fielded (Glonass, Galileo, Compass, SBAS) aggressively. In addition location technology is rapidly being incorporated into the mass-market consumer space thru implementation in cellular phones, autos, surveillance, tracking, and standalone navigation products – providing and enabling a whole new class of applications called Location Based Services (LBS). Effective development, manufacturing, and fielding of these systems requires new testing techniques that model real world expected conditions to provide assessments regarding performance, availability, accuracy. In this context, GNSS signal generation is key and the ability of such generators to duplicate real-world conditions is of particular importance. However, increasing the number of constellations, and therefore signals to be generated, raises considerable challenge as the hardware required. The common practice in this regard has been to use a standard computer front-end that controls one or many dedicated digital signal processing cards that carry out the required real-time signal processing. Increasing the number of satellite constellations/channels can therefore be handled by increasing the number of dedicated cards. This approach is quite direct and presents a relatively low risk. However, it can be costly since the required cards tend to be specialized (typically FPGA-based).
At École de technolgie supérieure, we have developed a working prototype of a multi-constellation simulator. In order to maximize the performance of this simulator prototype, this research projects aims at investigation the use of multi-core CPUs and/or high performance GPUs (Graphics Processing Units) to carry out more of the computation and signal processing tasks in the computer front-end thereby reducing the need for dedicated and costly real-time signal processing cards. Therefore, an optimal distribution of computational load between CPU/GPU and FPGA must be sought first at an architectural level then implemented and tested.
The student will collaborate with other team member to quantify the computational requirements for multi-channel GNSS signal generation (focus on a 12 channel GPS L1 scenario), determine the optimal CPU/GPU vs. FPGA distribution of the computational load and Implement and test the 12-channel GPS L1 scenario using the proposed distribution of (2)
