WP1.1.4 – Digital Compatible Modeling of Analog/RF/Optical Circuits

The intent of this project is to address the analog and silicon photonic modelling portion of a silicon photonic transceiver solution that will explore new and innovative metro reach terabit optical modems. In total there are five projects that combine to create the solution. These five project areas are silicon photonic design, high-speed electronic design, modelling, packaging, and test.
Optical transceiver simulation and verification is a challenging and time consuming task due to the complexity of models, diversity of simulators, and simulation intent.
The first part of the project is to address the problem of generation of a digital friendly library of analog models in system Verilog for Ciena’s analog IP to enable chip level verification. The models would provide different levels of abstraction and details tailored toward the intent of the simulation and verification. These models will be used for analog block level verification, chip level verification and test vector generation for production test and manufacturing.
The second part of the project intends to address the co-simulation of silicon photonic and electronic components and systems.

Faculty Supervisor:

Larbi Talbi;Mustapha Yagoub


Sabrine Ben Yochret


Ciena Canada


Computer science


Information and cultural industries




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